(1) Field of the invention
The present invention relates to a method of fabricating trench capacitor cell having a buried strap, and more particularly to a process for fabricating a trench capacitor cell with less polysilicon deposition and polishing steps.
(2) Description of the related art
A DRAM cell comprises a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor which are built in a semiconductor silicon substrate. There is an electrical contact between the source of a MOSFET and the storage node of the adjacent capacitor, forming a memory cell of the DRAM device. A large number of memory cells make up the cell arrays which combine with the peripheral circuit to construct DRAMs.
In recent years, the sizes of the MOSFETs and capacitors have become continuously smaller so that the packing densities of these DRAM devices have increased considerable. For example, a number of semiconductor manufacturing companies in the world have already begun mass production of 64 M bit or even 256 M bit DRAMs.
There are two types of the capacitors currently used for DRAM applications: stack capacitors and trench capacitors. As the sizes of the capacitors become smaller, so as the capacitance values of the capacitors are decreasing, that reduces the signal to noise ratio of the DRAM circuits, causing performance and reliability problems. The issue of maintaining or even increasing the surface area of the storage nodes or reducing the thickness of the dielectric layer is particularly important as the density of the DRAM arrays continues to increase for future generations of memory devices. When fabricating capacitors used for 16 Mbit DRAMs and beyond, increasing stack capacitor surface area becomes a top priority. Various shapes of stack capacitor structures have been used to address this issue. U.S. Pat. No. 5,185,282 to Lee et al. (the entire disclosure of which is herein incorporated by reference) provides a method of fabricating cup-shaped capacitor storage node. Another U.S. Pat. No. 5,021,357 to Taguchi et al. (the entire disclosure of which is herein incorporated by reference) supplies a method of fabricating fin structure capacitor electrode. These stack capacitor structures can effectively increase the capacitance values of the capacitors, however their manufacturing processes are too complicated and highly fastidious. They are difficult to be practically employed for mass-production. Most recently, H. Watanabe et al. in the paper "A new cylindrical capacitor using hemispherical grained Si (HSG-Si) for 256 Mb DRAMs" IEDM 92, pp. 259-262 (the entire disclosure of which is herein incorporated by reference) discloses a method of fabricating cylindrical stack capacitor electrode.
However, due to the already high density of the existing semiconductor devices little room is available for stack capacitors. Moreover, due to the high device density and minimum feature size it is necessary for processing sequences to be compatible with an ever increasing range of structures and materials. Therefore, trench capacitors with buried strap become a better choice for high density DRAM applications. U.S. Pat. No. 5,395,786 to Louis Hsu et al. of IBM and U.S. Pat. No. 4,694,561 to Lebowitz et al. of AT&T (the entire disclosures of which are herein incorporated by reference) both provide a method of fabricating trench capacitors. The trench capacitor structure has a major portion of its plates extending into rather than along the surface of a chip. The amount of the surface area required per capacitor is only the area of the trench at the surface of the chip that allows more densely packed DRAM arrays.
Referring now more particularly to FIG. 1, there are sown a typical trench capacitor processing sequences. First, an oxide layer 12 and a nitride layer 14 are continuously formed on a silicon substrate 10. The oxide layer 12 and nitride layer 14 layers are then partially etched to open a process window for forming a trench by conventional lithography and plasma-etching techniques. Then, the exposed silicon substrate is also etched to form a as shown in FIG. 1A. Next, an oxide/nitride/oxide (ONO) capacitor dielectric layer 18 is deposited inside the trench. A first polysilicon layer 20 as storage node is then deposited to fill the bottom of the trench. Thereafter, dielectric collars 22 are formed on the interior sidewalls of the trench as shown in FIG. 1A. A second polysilicon layer 24 is next deposited inside the trench and aligned with the dielectric collars as shown in FIG. 1B. Next, the second polysilicon is chemical mechanical polished or etchback to form a second polysilicon stud 24a inside the trench. The dielectric collars 22a are then recessed to expose the contact area for the capacitor as shown in FIG. 1C. Next, a third polysilicon layer 26 is deposited and polished overlaying the second polysilicon stud as shown in FIG. 1D. Finally, the third polysilicon layer 26a is etchback to a height slightly lower than the substrate surface to complete the trench capacitor formation.
There are some drawbacks for the conventional trench capacitor fabricating process:
1. The process sequences are complicated and tedious. It needs three polysilicon depositions and two CMP polishings to form a trench capacitor that increases the possibility of wafer contamination. PA1 2. It is also a time consuming process that increases the production cost as well.
Therefore, the present invention discloses an easy and manufacturable method to fabricate trench capacitors for high density DRAM applications.